Bcd Adder and Multiplier Using Reversible Logic Design

Filters are widely used in the world of communication and computation. To design a finite impulse response (FIR) filter that satisfies all the required conditions is a challenge. Power consumption by the multiplier and adder blocks in the architecture is the prime cause for concern in FIR design. In this paper, design of an FIR filter entirely using Reversible logic is presented. Reversible logic is emerging as a promising computing paradigm having widespread areas of application. It is based on the fundamental that zero energy dissipation would be achieved if the design is made of reversible gates. Furthermore, majority of the design is made of Peres gate which has the least quantum cost of all the existing reversible gates. Thus, this paper presents the first and novel approach in realizing an FIR filter that can overcome the problem of power dissipation. The first and foremost approach in designing a low pass FIR filter entirely using reversible logic is presented in this paper. The design is the most novel for it, dominantly makes use of a Peres Gate (quantum cost = 4) in the realization of the multiplier and adder blocks which form major components of the FIR filter block. Power dissipation, the most vital issue in the design of a circuit, can be resolved to the maximum extent by following the proposed implementation.